This invention relates in general to first-in first-out ("FIFO") memory devices and methods for accessing the device and in particular, to a pipelined FIFO device and method with improved access time.
FIFOs are accessed by means of read signals. The access time of a FIFO is the delay time from the point in time when the read signal is applied to the FIFO to the subsequent point in time when valid data appears at the output of the FIFO. A FIFO typically has a memory array, word lines which supply the address signals for selecting the location in the array from which data is to be read, and bit lines for supplying the data read from the array to the FIFO output. Traditionally, FIFOs have been accessed in a manner similar to that for static random access memories. The access procedure includes pulling up the word lines connected to a memory array of the FIFO. The data in the array then appears on bit lines where the bit line data is amplified by a sense amplifier before it is sent to an output driver for driving the FIFO output. Such procedure requires considerable time so that conventional FIFOs have long access times. The slow access of memory devices such as conventional FIFOs frequently becomes the bottleneck in a computer system and determines the speed of the system. It is therefore desirable to provide FIFOs with improved access time.